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101 innovation drive san jose, ca 95134 www.altera.com mnl-01061-1.0 reference manual max v cpld development board subscribe max v cpld development board reference manual
max v cpld development board reference manual january 2011 altera corporation ? 2011 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix are reg. u.s. pat. & tm. off. and/or trademarks of altera corporation in the u.s. and other countries. all other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance with altera?s standard warranty, but reserv es the right to make changes to any products and services at any time without notice . altera assumes no responsibility or liability arising out of the application or us e of any information, product, or servic e described herein except as expressly ag reed to in writing by altera. altera customers are advised to obtain the latest version of device spec ifications before re lying on any published information and bef ore placing orders for products or services.
january 2011 altera corporation max v cpl d development board reference manual contents chapter 1. overview introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 board component blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 development board block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 handling the board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 chapter 2. board components introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 board overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2 featured device: max v cpld . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 i/o resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 configuration, status, and setup elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 cpld configuration over embedded usb-blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 cpld configuration using external usb-blas ter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ?6 status elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6 setup elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?7 clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?7 connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?8 gpio headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?8 pc speaker header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?10 dc motor headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?11 general user input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?13 user-defined push-button switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?13 user-defined leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?13 off-chip eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 i 2 c eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 spi eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?15 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?16 statement of china-rohs compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?16 additional information document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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iv contents max v cpld development board reference manual january 2011 altera corporation
january 2011 altera corporation max v cpl d development board reference manual 1. overview introduction this document describes the ha rdware features of the max ? v cpld development board, including the detailed pin-out and component reference information required to create custom cpld designs that inte rface with all components of the board. general description the max v cpld development board provides a hardware platform for developing and prototyping low-cost, low-power cpld designs, as well as to demonstrate the features of the max v cpld device. to facilitate the development of max v cp ld designs, the board provides connectors to interface to external functions or devices. f for more information on the max v cpld device family, refer to the max v device handbook . board component blocks the board features the following major component blocks: max v cpld 5M570ZF256C5N in a 2 56-pin fineline bga (fbga) package 570 logic elements (les) 440 equivalent macrocells 8,192-bits user flash memory (ufm) 4 global clocks 159 user i/os 1.8-v core power max ii epm240m100c4n cpld in the 100-pin micro fbga (mbga) package on-board configuration circuitry embedded usb-blaster tm for use with the quartus ? ii programmer on-board connectors type-b usb connector (as power source and communication port) two general purpose i/o (gpio) 220-pin 0.1-inch expansion headers one 4-pin pc speaker header two 23-pin dc motor headers on-board clocking circuitry 10-mhz single-ended external oscillator
1?2 chapter 1: overview development board block diagram max v cpld development board reference manual january 2011 altera corporation general user i/o leds and display two cpld user leds one usb status led one power status led push-button switches two user-defined push-button switches one capacitor sense push-button switch mechanical 4.1? 3.1? board development board block diagram figure 1?1 shows the block diagram of the max v cpld development board. handling the board when handling the board, it is important to observe the following static discharge precaution: c without proper anti-static handling, the board can be damaged. therefore, use anti-static handling precautions when touching the board. figure 1?1. max v cpld development board block diagram dc motor header 1 epm240m100 embedded usb-blaster usb 2.0 x1 x9 x2 jtag chain gpio header 2 ep5m570zf256n spi x4 user leds push-button switches x2 x36 i 2 c x2 10 mhz oscillator gpio header 1 x36 pc speaker header capacitor sense push-button switch x8 x9 dc motor header 2 eeprom eeprom
january 2011 altera corporation max v cpl d development board reference manual 2. board components introduction this chapter introduces the major comp onents on the max v cpld development board. figure 2?1 illustrates major component locations and table 2?1 provides a brief description of all component features of the board. 1 a complete set of schematics, a physical layout database, and gerber files for the development board reside in the max v cpld development kit documents directory. f for information about powering up the board and installing the demonstration software, refer to the max v cpld development kit user guide . this chapter consists of the following sections: ?board overview? ?featured device: max v cpld? on page 2?3 ?configuration, status, and setup elements? on page 2?5 ?clock circuitry? on page 2?7 ?connectors? on page 2?8 ?general user input/output? on page 2?13 ?off-chip eeprom? on page 2?14 ?power supply? on page 2?16 ?statement of china-rohs compliance? on page 2?16
2?2 chapter 2: board components board overview max v cpld development board reference manual january 2011 altera corporation board overview this section provides an overview of the max v cpld development board, including an annotated board im age and component descriptions. figure 2?1 provides an overview of the development board features. table 2?1 describes the components and lists their corresponding board references. figure 2?1. overview of the max v cpld development board features max v cpld (u5) 10-mhz single-ended external oscillator (j1) user leds (d7, d8) gpio headers (j6, j7) usb type-b connector (j4) motor control header 1 (j5) power led (d1) user push-button switches (s1, s2) max ii cpld epm240m100c4n (for embedded usb-blaster) (u4) motor control header 2 (j10) speaker header (j9) footprint for i 2 c eeprom (u6) footprint for spi eeprom (u8) power regulator (u7) usb led (d3) capacitor sense button (cpb1) var_vccio voltage output selection jumper (u7) table 2?1. max v cpld development board components (part 1 of 2) board reference type description featured device u5 cpld max v 5M570ZF256C5N, 256-pin fbga. configuration, status, and setup elements j4 usb type-b connector connects the usb cable to the computer to enable embedded usb-blaster jtag. the connector also supplies power to the board through a usb cable when the cable is connected to a pc usb slot at the other end.
chapter 2: board components 2?3 featured device: max v cpld january 2011 altera corporation max v cpl d development board reference manual featured device: max v cpld the max v cpld development board features the max v cpld 5M570ZF256C5N device (u5) in a 256-pin fbga package. table 2?2 describes the features of the max v cpld 5M570ZF256C5N device. f for more information about max v cpld device family, refer to the max v device handbook . u3 usb 2.0 phy a ftdi usb 2.0 phy device to configure the cpld over embedded usb-blaster. u4 cpld max ii cpld epm240m100. j13, j14 jtag header footprint (at the bottom of the board) to mount a jtag header. the header allows direct-access to devices in the jtag connection. d1 power led illuminates when 5-v usb power is present. d3 usb led illuminates to indicate usb-jtag activity. clock circuitry j1 10-mhz oscillator 10-mhz single-ended input clock for the max v cpld. x1 6-mhz oscillator 6-mhz input clock for the ftdi usb 2.0 phy device. y1 24-mhz oscillator 24-mhz input clock for the max ii cpld epm240m100. connectors j6, j7 gpio headers two general-purpose 2x40-pin 0.1-inch expansion headers. j9 pc speaker header a 4-pin pc speaker header which connects to the max v cpld i/o bank 2. j5, j10 dc motor headers two motor headers which connects to the max v cpld i/o bank 2. general user input/output d7, d8 user leds two user leds. illuminates when driven low. s1, s2 user push-button switches two user push-button switches. driven low when pressed. cpb1 capacitor sense button one capaciti ve touch-sense user-defined button. off-chip eeprom u6 i 2 c eeprom footprint to install an i 2 c serial eeprom u8 spi eeprom footprint to install a spi eeprom. table 2?1. max v cpld development board components (part 2 of 2) board reference type description table 2?2. max v cpld 5M570ZF256C5N device features equivalent les user flash memory (bits) user i/os global clocks package type 570 8192 159 4 256-pin fbga
2?4 chapter 2: board components featured device: max v cpld max v cpld development board reference manual january 2011 altera corporation table 2?3 lists the max v cpld device comp onent reference and manufacturing information. i/o resources the 5M570ZF256C5N device support two i/o banks and each of these banks support all the lvttl, lvcmos, lvds, and rsds standards. figure 2?2 illustrates the bank organization for the 5M570ZF256C5N device in a 256-pin fbga package. table 2?4 lists the max v cpld device pin count and usage by function on the development board. table 2?3. max v cpld device component reference and manufacturing information board reference description manufacturer manufacturing part number manufacturer website u5 max v cpld, 256-pin fbga package, 570 les, lead-free. altera corporation 5M570ZF256C5N www.altera.com figure 2?2. 5M570ZF256C5N device i/o bank diagram (note 1) note to figure 2?2 : (1) this figure is a top view of the silicon die and is a graphical representation only. refer to the pin list and the quartus ii software for exact pin locations. i/o bank 1 i/o bank 2 5M570ZF256C5N table 2?4. max v cpld device i/o pin count and usage (part 1 of 2) function i/o standard i/o count special pins 40-pin gpio header a 3.3-v cmos 36 ? 40-pin gpio header b 1.2-v to 3.3-v 36 ? pc speaker header 8 ? dc motor headers 18 ?
chapter 2: board components 2?5 configuration, status, and setup elements january 2011 altera corporation max v cpl d development board reference manual configuration, status , and setup elements this section describes the board's configuration, status, and setup elements. configuration the max v cpld development board supports the following device configuration methods: embedded usb-blaster is the default method for configuring the cpld at any time using the quartus ii programmer in jtag mode with the supplied usb cable. external usb-blaster for configuring the cpld using a jtag connector. to use this optional method to configure the cpld, yo u have to mount the jtag connector or header to the back of the board. cpld configuration over embedded usb-blaster the usb-blaster is implemented using a usb type-b connector (j4), a ftdi usb 2.0 phy device (u3), and an al tera max ii cpld epm240m100 (u4). this allows the configuration of the max v cpld using a usb cable which connects between the usb port on the board (j4) and a usb port of a pc running the quartus ii software. the jtag chain is normally mastered by the embedded usb-blaster found in the max ii cpld epm240m100. push-buttons 3.3-v cmos 2 push-button 2: dev_clrn user leds 2 ? i 2 c eeprom 2 ? spi eeprom 4 ? clock 1 ? device i/o total: 109/159 table 2?4. max v cpld device i/o pin count and usage (part 2 of 2) function i/o standard i/o count special pins
2?6 chapter 2: board components configuration, status, and setup elements max v cpld development board reference manual january 2011 altera corporation figure 2?3 illustrates an exmaple of the jtag chain connection. the primary configuration mode for the max v cpld is via jtag using the max ii configuration controller design (embedded usb-blaster). the board also includes a jtag connector which interfaces directly to the max v cpld as the alternate source for configuration. cpld configuration using external usb-blaster the jtag programming header (j13) provid es another method for configuring the cpld using an external us b-blaster device with the quartus ii programmer running on a pc. the external usb-blaster connects to the board through the jtag connector. figure 2?3 illustrates the jtag chain. status elements this section describes the status elements. the development board includes two status leds which connects to the max v cpld. table 2?5 lists the led board references, names, and functional descriptions. figure 2?3. jtag chain max v cpld 5M570ZF256C5N tck tms tdi tdo jtag 2 x 5 header max ii epm240m100 tck tms tdi tdo jtag 2 x 5 header tck tms tdi tdo embedded usb-blaster gpio (tck) gpio (tms) gpio (tdo) gpio (tdi) tck tms tdi tdo usb phy (connector not mounted) (connector not mounted) table 2?5. board-specific leds board reference led name description d1 power blue led. illuminates when power is active. d3 usb green led. illuminates when the embedded usb-blaster is in use. driven by the max ii cpld epm240m100.
chapter 2: board components 2?7 clock circuitry january 2011 altera corporation max v cpl d development board reference manual table 2?6 lists the board-specific leds component references and manufacturing information. setup elements the development board does not have any setup elements. 1 to power-up the board, ensure that the var_vccio jumper is set to 3.3 v before plugging the usb cable into the usb type-b connector (j4). clock circuitry the development board includes a single-end ed clock input on a 4-pin through-hole socket. to replace the clock input with a different frequency oscillator, unplug the current oscillator from the board and plug th e desired oscillator into the 4-pin socket. figure 2?4 shows the max v cpld development board clock input. the development board also includes a 6-mhz crystal oscillator which provides the input clock for the usb 2.0 phy device. table 2?16 lists the oscillator component reference and the manufacturing information. table 2?6. board-specific leds component references and manufacturing information board reference description manufacturer manufacturer part number manufacturer website d1 blue led lite-on ltst-c170tbkt www.liteon.com d3 green leds lumex inc. sml-lxt0805gw-tr www.lumex.com figure 2?4. max v cpld development board clock input 5M570ZF256C5N single-ended clock 10 mhz table 2?7. oscillator component reference and manufacturing information board reference description manufacturer manufacturer part number manufacturer website j1 10-mhz oscillator, 3.3 v, cmos, 12.7 mm 12.7 mm, 1/2-sz, 30 ppm. abracon corporation achl-10.000mhz-ek www.abracon.com x1 6-mhz crystal oscillator, 20pf smd. cts corporation ats060sm-t www.ctscorp.com y1 24-mhz oscillator, 3.3 v, cmos smd 3.2 mm 2.5 mm, 50 ppm. abracon corporation ase-24.000mhz-et www.abracon.com
2?8 chapter 2: board components connectors max v cpld development board reference manual january 2011 altera corporation connectors this section describes the connectors available on the development board. gpio headers there are two general-purpose 220-pin 0.1-inch expansion headers to allow the addition of daughtercards for supplem entary board features and functions. table 2?15 lists the gpio header a schematic signal names and their corresponding max v cpld device pin numbers. table 2?8. gpio header a schematic signal names and functions board reference description schematic signal name i/o standard max v cpld device pin number j6.1 gpio connector a pin agpio_1 3.3-v p2 j6.2 gpio connector a pin agpio_2 m4 j6.3 gpio connector a pin agpio_3 l4 j6.4 gpio connector a pin agpio_4 n3 j6.5 gpio connector a pin agpio_5 n2 j6.6 gpio connector a pin agpio_6 n1 j6.7 gpio connector a pin agpio_7 m3 j6.8 gpio connector a pin agpio_8 m2 j6.9 gpio connector a pin agpio_9 m1 j6.10 gpio connector a pin agpio_10 l3 j6.11 power 5vin_conn 5-v ? j6.12 ground gnd ?? j6.13 gpio connector a pin agpio_11 3.3-v l1 j6.14 gpio connector a pin agpio_12 l2 j6.15 gpio connector a pin agpio_13 k2 j6.16 gpio connector a pin agpio_14 k3 j6.17 gpio connector a pin agpio_15 j3 j6.18 gpio connector a pin agpio_16 k1 j6.19 gpio connector a pin agpio_17 j1 j6.20 gpio connector a pin agpio_18 j2 j6.21 gpio connector a pin agpio_19 h2 j6.22 gpio connector a pin agpio_20 h3 j6.23 gpio connector a pin agpio_21 g3 j6.24 gpio connector a pin agpio_22 h1 j6.25 gpio connector a pin agpio_23 g1 j6.26 gpio connector a pin agpio_24 g2 j6.27 gpio connector a pin agpio_25 f2 j6.28 gpio connector a pin agpio_26 f3 j6.29 power 3.3vin_conn ? j6.30 ground gnd ??
chapter 2: board components 2?9 connectors january 2011 altera corporation max v cpl d development board reference manual table 2?15 lists the gpio header b schematic signal names and their corresponding max v cpld device pin numbers. j6.31 gpio connector a pin agpio_27 3.3-v e3 j6.32 gpio connector a pin agpio_28 f1 j6.33 gpio connector a pin agpio_29 e1 j6.34 gpio connector a pin agpio_30 e2 j6.35 gpio connector a pin agpio_31 d2 j6.36 gpio connector a pin agpio_32 d3 j6.37 gpio connector a pin agpio_33 c3 j6.38 gpio connector a pin agpio_34 d1 j6.39 gpio connector a pin agpio_35 e4 j6.40 gpio connector a pin agpio_36 c2 table 2?8. gpio header a schematic signal names and functions board reference description schematic signal name i/o standard max v cpld device pin number table 2?9. gpio header b schematic signal names and functions board reference description schematic signal name i/o standard max v cpld device pin number j7.1 gpio connector b pin bgpio_p_1_r variable vccio voltage (1.2-v to 3.3-v) d15 j7.2 gpio connector b pin bgpio_n_1_r c14 j7.3 gpio connector b pin bgpio_p_2_r d16 j7.4 gpio connector b pin bgpio_n_2_r c15 j7.5 gpio connector b pin bgpio_p_3_r e15 j7.6 gpio connector b pin bgpio_n_3_r d13 j7.7 gpio connector b pin bgpio_7 b14 j7.8 gpio connector b pin bgpio_8 c12 j7.9 gpio connector b pin bgpio_9 e16 j7.10 gpio connector b pin bgpio_10 e14 j7.11 power 5vin_conn ? j7.12 ground gnd ? j7.13 gpio connector b pin bgpio_11 f13 j7.14 gpio connector b pin bgpio_12 f16 j7.15 gpio connector b pin bgpio_13 f15 j7.16 gpio connector b pin bgpio_14 f14 j7.17 gpio connector b pin bgpio_15 g16 j7.18 gpio connector b pin bgpio_16 g15 j7.19 gpio connector b pin bgpio_17 g14 j7.20 gpio connector b pin bgpio_18 h16 j7.21 gpio connector b pin bgpio_19 h15 j7.22 gpio connector b pin bgpio_20 h14 j7.23 gpio connector b pin bgpio_21 j16
2?10 chapter 2: board components connectors max v cpld development board reference manual january 2011 altera corporation table 2?16 lists the gpio headers component reference and the manufacturing information. pc speaker header the development board includes one pc speaker header which connects to the max v cpld i/o bank 2. the speaker header also supports a compatible standard four-pin motherboard speaker. j7.24 gpio connector b pin bgpio_22 variable vccio voltage (1.2-v to 3.3-v) j15 j7.25 gpio connector b pin bgpio_23 j14 j7.26 gpio connector b pin bgpio_24 k16 j7.27 gpio connector b pin bgpio_25 k15 j7.28 gpio connector b pin bgpio_26 k14 j7.29 power 3.3vin_conn 3.3-v ? j7.30 ground gnd ?? j7.31 gpio connector b pin bgpio_27 variable vccio voltage (1.2-v to 3.3-v) l16 j7.32 gpio connector b pin bgpio_28 l15 j7.33 gpio connector b pin bgpio_29 l14 j7.34 gpio connector b pin bgpio_30 m16 j7.35 gpio connector b pin bgpio_31 m15 j7.36 gpio connector b pin bgpio_32 m14 j7.37 gpio connector b pin bgpio_33 l13 j7.38 gpio connector b pin bgpio_34 m13 j7.39 gpio connector b pin bgpio_35 n14 j7.40 gpio connector b pin bgpio_36 n13 table 2?9. gpio header b schematic signal names and functions board reference description schematic signal name i/o standard max v cpld device pin number table 2?10. gpio headers component reference and manufacturing information board reference description manufacturer manufacturer part number manufacturer website j6, j7 gpio headers jmsconn technology 217040se www.jmsconn.com
chapter 2: board components 2?11 connectors january 2011 altera corporation max v cpl d development board reference manual table 2?15 lists the speaker header schematic signal names and their corresponding max v cpld device pin numbers. table 2?16 lists the speaker header component reference and the manufacturing information. dc motor headers the development board includes two dc motor headers which are driven by six open-drain i/os from the max v cpld. the headers can directly drive micro dc motor and also provides two channels for dc motor encoder to measure the motor?s rotation speed. table 2?11. speaker header schematic signal names and functions board reference description schematic signal name i/o standard max v cpld device pin number j9.1 speaker header i/o pin max_spk_0 variable vccio voltage (1.2-v to 3.3-v) n15 speaker header i/o pin max_spk_1 n16 speaker header i/o pin max_spk_2 p15 speaker header i/o pin max_spk_3 p14 speaker header i/o pin max_spk_4 h12 speaker header i/o pin max_spk_5 j12 speaker header i/o pin max_spk_6 a8 speaker header i/o pin max_spk_7 a7 j9.4 power var_vccio ? j9.3 ground gnd ?? table 2?12. speaker header component reference and manufacturing information board reference description manufacturer manufacturer part number manufacturer website j9 0.025 inches (0.64 mm) square post header samtec tsw-104-07-g-s www.samtec.com ? 4-pin, 2-wire motherboard speaker (1) pc parts collection 20503 www.pcpartscollection.com note to table 2?12 : (1) this component is a compatible unit wh ich can be used on the development board. the max v cpld development kit does not incl ude this component.
2?12 chapter 2: board components connectors max v cpld development board reference manual january 2011 altera corporation table 2?15 lists the motor headers schematic signal names and their corresponding max v cpld device pin numbers. table 2?16 lists the motor headers component reference and the manufacturing information. table 2?13. motor headers schematic signal names and functions board reference description schematic signal name i/o standard max v cpld device pin number j5.3 motor header 1 i/o pin max_motor_1_0 variable vccio voltage (1.2-v to 3.3-v) b1 motor header 1 i/o pin max_motor_1_1 b3 motor header 1 i/o pin max_motor_1_2 a2 motor header 1 i/o pin max_motor_1_3 a6 motor header 1 i/o pin max_motor_1_4 a4 motor header 1 i/o pin max_motor_1_5 a5 j5.2 motor header 1 feedback signal a motor_1_fb_a c7 j5.4 motor header 1 feedback signal b motor_1_fb_b c6 j5.6 motor header 1 control signal motor_1_fb_ctrl c5 j5.1 power var_vccio ? j5.5 ground gnd ? j10.3 motor header 2 i/o pin max_motor_2_0 a10 motor header 2 i/o pin max_motor_2_1 a15 motor header 2 i/o pin max_motor_2_2 a11 motor header 2 i/o pin max_motor_2_3 a13 motor header 2 i/o pin max_motor_2_4 a12 motor header 2 i/o pin max_motor_2_5 b16 j10.2 motor header 2 feedback signal a motor_2_fb_a d12 j10.4 motor header 2 feedback signal b motor_2_fb_b b12 j10.6 motor header 2 control signal motor_2_fb_ctrl variable vccio voltage (1.2-v to 3.3-v) e13 j10.1 power va_vccio ? j10.5 ground gnd ? table 2?14. motor headers component reference and manufacturing information board reference description manufacturer manufacturer part number manufacturer website j10 surface mount terminal strip samtec tsm-103-01-l-dv-tr www.samtec.com ? dc motor (30:1 micro metal gearmotor) (1) cytron technologies mo-spg-10-30k www.cytron.com.my ? dc motor encoder (encoder for pololu wheel 4219 mm) (1) pololu sn-en-pw4219 www.cytron.com.my note to table 2?14 : (1) this component is a compatible unit wh ich can be used on the development board. the max v cpld development kit does not incl ude this component.
chapter 2: board components 2?13 general user input/output january 2011 altera corporation max v cpl d development board reference manual general user input/output this section describes the user i/o interface to the cpld, including the push-buttons and status leds. user-defined push-button switches the development board includes two user-defined push-button switches. board references s1 ( user_pb1 ) and s2 ( user_pb0 ) are push-button switches that allow you to interact with the max v cpld device. there is no board-specific function for these user-defined push-button switches. table 2?15 lists the user-defined push-button switch schematic signal names and their corresponding max v cpld device pin numbers. table 2?16 lists the user-defined push-button switch component reference and the manufacturing information. user-defined leds the development board includes two general purpose leds. board references d7 ( user_led1 ) and d8 ( user_led0 ) are user-defined leds which allow status and debugging signals to be driven to the leds from the cpld designs loaded into the max v cpld device. there is no board-specific function for these leds. table 2?17 lists the user-defined led schematic signal names and their corresponding max v cpld pin numbers. table 2?15. user-defined push-button switch schematic signal names and functions board reference description schematic signal name i/o standard max v cpld device pin number s2 user-defined push-button switch. when the switch is pressed and held down, the device pin is set to logic 0; when the switch is released, the device pin is set to logic 1. user_pb0 3.3-v m9 s1 user_pb1 r3 table 2?16. user-defined push-button switch component reference and manufacturing information board reference description manufacturer manufacturer part number manufacturer website s1, s2 push-button switches dawning precision co., ltd. ts-a02sa-2-s100 www.dawning2.com.tw table 2?17. user-defined led schematic signal names and functions board reference description schematic signal name i/o standard max v cpld device pin number d8 user-defined leds. driving a logic 0 on the i/o port illuminates the led. driving a logic 1 on the i/o port turns off the led. user_led0 3.3-v p4 d7 user_led1 r1
2?14 chapter 2: board components off-chip eeprom max v cpld development board reference manual january 2011 altera corporation table 2?18 lists the user-defined led component reference and the manufacturing information. off-chip eeprom this section describes the board's eeprom interface support and also their signal names, types, and connectivity relative to the max v cpld device. the board include footprints for you to mount the following eeprom device: i 2 c eeprom spi eeprom 1 the max v cpld development board only provide the eeprom device footprints. however, the board test system eeprom function is developed based on the eeprom components described in this section. i 2 c eeprom board reference u6 is a footprint to mount an i 2 c eeprom device onto the development board. table 2?19 lists the i 2 c eeprom device pin assignments, signal names, and functions. the signal names and types are relative to the max v cpld device in terms of i/o setting and direction. table 2?18. user-defined led component reference and manufacturing information board reference device description manufacturer manufacturer part number manufacturer website d7, d8 green leds lumex, inc. sml-lx1206gc-tr www.lumex.com table 2?19. i 2 c eeprom pin assignments, schematic signal names, and functions board reference description schematic signal name i/o standard max v cpld device pin number u6.1 clock to synchronize the data transfer to and from the device. i2c_prom_scl 3.3-v t13 u6.2 bidirectional serial data pin to transfer addresses and data into and out of the device. i2c_prom_sda r13 u6.5 write-protect pin. tied to v ss : normal operation (read or write to the entire memory of 000-3ff). tied to v cc : write operation disabled (the entire memory is write-protected). read operation is not affected. i2c_prom_wp ?
chapter 2: board components 2?15 off-chip eeprom january 2011 altera corporation max v cpl d development board reference manual table 2?20 lists the i 2 c eeprom component reference and manufacturing information. spi eeprom board reference u8 is a footprint to mount a spi eeprom device onto the development board. table 2?21 lists the spi eeprom pin assignments, signal names, and functions. the signal names and types are relative to the max v cpld device in terms of i/o setting and direction. table 2?22 lists the spi eeprom component reference and manufacturing information. table 2?20. i 2 c eeprom component reference and manufacturing information board reference description manufacturer manufacturing part number manufacturer website u6 8-kbit eeprom, 256 8-bit memory (1) microchip 24lc08bt-i/ot www.microchip.com note to table 2?20 : (1) this component is a compatible unit wh ich can be used on the development board. the max v cpld development kit does not incl ude this component. table 2?21. spi eeprom pin assignments, schematic signal names, and functions board reference description schematic signal name i/o standard max v cpld device pin number u8.1 spi chip select signal spi_csn 3.3-v r14 u8.2 spi data in signal (master-in-slave-out) spi_miso t15 u8.5 spi data out signal (master-out-slave-in) spi_mosi p13 u8.6 spi clock signal spi_sck r16 table 2?22. spi eeprom component reference and manufacturing information board reference description manufacturer manufacturing part number manufacturer website u8 256-kbit serial eeprom (1) microchip 25lc256-i/st www.microchip.com note to table 2?22 : (1) this component is a compatible unit wh ich can be used on the development board. the max v cpld development kit does not incl ude this component.
2?16 chapter 2: board components power supply max v cpld development board reference manual january 2011 altera corporation power supply the development board is powered up through a usb cable. the blue led illuminates when the board is powered up. alternatively, you can also power-up the board by connecting three 1.5-v batteries in se ries (to obtain 4.5 v) through connectors batt+ and batt- . 1 once you plug the usb cable into the bo ard?s usb connector and connect the other end of the cable to a pc usb slot, the boar d disconnects the battery supply and switch over to obtain power supply from the usb cable. table 2?23 lists the power rails. table 2?24 lists the power rail component refe rence and manufacturing information. statement of china-rohs compliance table 2?25 lists hazardous substances included with the kit. table 2?23. power rails rail schematic signal name voltage (v) device pin description 1 1.8_vccint 1.8 vccint cpld core voltage 2 var_vccio 1.2 ? 3.3 vccio cpld i/o bank 2 variable voltage 3 3.3v 3.3 vccio power for i/o bank 1 and eeprom 4 5v 5.0 5v_usb power-up usb peripheral table 2?24. power supply rail component reference and manufacturing information board reference description manufacturer manufacturing part number manufacturer website u7 400 ma, 2.25 mhz synchronous step-down dc/dc converter linear technology ltc3670 www.linear.com table 2?25. table of hazardous substances? name and concentration notes (1) , (2) part name lead (pb) cadmium (cd) hexavalent chromium (cr6+) mercury (hg) polybrominated biphenyls (pbb) polybrominated diphenyl ethers (pbde) max v cpld development board x* 0 0 0 0 0 type a-b usb cable 0 0 0 0 0 0 notes to table 2?25 : (1) 0 indicates that the concentration of th e hazardous substance in all homogeneous materials in the parts is below the relevan t threshold of the sj/t11363-2006 standard. (2) x* indicates that the concentration of th e hazardous substance of at least one of all homogeneous materials in the parts is above the relevant threshold of the sj/t11363- 2006 standard, but it is exempted by eu rohs.
january 2011 altera corporation max v cpl d development board reference manual additional information this chapter provides additional info rmation about the document and altera. document revision history the following table shows the revision history for this document. how to contact altera to locate the most up-to-date informat ion about altera products, refer to the following table. date version changes january 2011 1.0 initial release. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note to table: (1) you can also contact yo ur local altera sales office or sales representative.
info?2 additional informationadditional information typographic conventions max v cpld development board reference manual january 2011 altera corporation typographic conventions the following table shows the typographic conventions this document uses. visual cue meaning bold type with initial capital letters indicate command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, di sk drive names, file names, file name extensions, software utility names, and gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicate document titles. for example, stratix iv design guidelines . italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, and .pof file. initial capital letters indicate keyboard keys and menu names. for example, the delete key and the options menu. ?subheading title? quotation marks indicate references to sections within a document and titles of quartus ii help topics. for example, ?typographic conventions.? courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . the suffix n denotes an active-low signal. for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). r an angled arrow instructs you to press the enter key. 1., 2., 3., and a., b., c., and so on numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. a question mark directs you to a software help system with related information. f the feet direct you to another document or website with related information. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. the envelope links to the email subscription management center page of the altera website, where you can sign up to receive update notifications for altera documents.

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